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AL128 data sheets
AL128 april 2, 1999 2 contents 1.0 features ________________________ 3 2.0 applications _____________________ 4 3.0 general description _______________ 4 4.0 pinout diagram __________________ 5 5.0 pin definition and description ______ 6 6.0 functional description ___________ 12 6.1 input interface ___________________ 12 6.1.1 24-bit rgb _______________________ 13 6.1.2 vafc ___________________________ 13 6.1.3 feature connector _________________ 14 6.1.4 sampling (pixel) clock _____________ 14 6.2 hardware and software control modes ________________________________ ___ 15 6.3 video timing ____________________ 15 6.4 supported resolutions _____________ 17 6.5 flicker filter _____________________ 18 6.6 overscan/underscan control _______ 18 6.7 pan and position control ___________ 18 6.8 zoom feature ____________________ 18 6.9 frame buffer management _________ 19 6.10 digital video encoder ____________ 19 6.11 push button interface/osd ________ 19 6.12 memory control timing __________ 20 6.13 i 2 c programming ________________ 23 7.0 electrical characteristics __________ 26 7.1 recommended operating conditions _ 26 7.2 characteristics ___________________ 26 8.0 AL128 register definition _________ 27 8.1 index of the control registers _______ 27 8.2 control register description ________ 28 8.3 AL128 plug & play hardware table _ 38 9.0 board design and layout considerations ______________________ 40 9.1 grounding _______________________ 40 9.2 power planes _____________________ 40 9.3 power supply decoupling __________ 40 9.4 digital signal and clock interconnect 40 9.5 analog signal interconnect _________ 41 9.6 component placement _____________ 41 10.0 mechanical drawing _____________ 42 11.0 power consumption ______________ 44
AL128 april 2, 1999 3 AL128 plug and play vga to ntsc/pal converter 1.0 features convert non-interlaced vga or macintosh video into interlaced tv format (ntsc/pal) analog rgb output for scart interface highly integrated design with built-in ntsc/pal encoder, adc, dac and sram broadcast tv quality high clarity 5-line anti-flicker filter 8 levels of sharpness control plug and play with no need for software or micro-controller supports up to full 1024x768 vga resolution automatically supports scan rate from 50 hz up to 100 hz linear vertical and horizontal overscan/ underscan control zoom and freeze controls four-touch-button interface with on-screen- menu (on tv) to control all key functions horizontal and vertical position centering control optional digital 24-bit rgb/vafc interface for best quality power down feature controlled by software or hardware full programmability via i 2 c interface picture panning control brightness control built-in color bar simultaneous display on pc and tv monitors single 5-volt support thin, small lqfp package for pcmcia or notebooks. 28x28 pqfp available upon request timing generating 2 c 8-bit adc mux 9-bit dac 8-bit adc 8-bit adc 9-bit dac 9-bit dac memory management unit memory configuration setup digital video processor digital tv encoder video memory push button interface ghsout gvsout tvclk xout1 xout2 sda xin1 xin2 scl select menu inc dec vrt vrb aden r g b digital r, g, b acmp / r ay / g ac / b rset vref comp md mq mwenl mwenh mwrst mren mrrst mwclk mrclk memconf memtype /reset /reset /pwrdn pal intype rgb field memory ghsync gvsync ghsdiv gclk AL128-01 i 2 c i 2 c interface i 2 caddr
AL128 april 2, 1999 4 2.0 applications pc ready multimedia tv tv output for laptop, network, entertainment pc net browser/set-top box internet tv vga add-on card with tv output vga to tv converter box 3.0 general description the AL128 pc to tv scan converter chip accepts graphic data up to 1024x768 resolution from pc and macintosh graphics controllers and converts it into broadcast- quality ntsc or pal tv signals. in addition to analog rgb, 24-bit digital rgb data can be input to maintain the best video quality and avoid noise problems. this new chip is pin-to- pin compatible with the averlogic al100 but provides analog rgb output for scart implementation. an integrated high-quality anti-flicker filter (smartfilter ? ) removes the unpleasant flicker caused by the interlaced display of high contrast graphics while maintaining the original clarity and sharpness of informative data such as natural pictures and text. with 512kbytes of memory, plug-and-play is achieved by automatically detecting the scan rate and resolution of the incoming graphic signals without the use of software. with less memory than other solutions on the market, high resolution data is processed and stored by using a complex and proprietary buffer management system. no compromise is made at all with video quality by using either compression or sub-sampling algorithms. the major functions of the AL128 can be accessed using four push buttons combined with the on-screen-menu feature, eliminating the cost of a micro-controller and complex control panel. the superior quality scaling algorithm, which reduces the jagged-edge artifacts from line dropping, can smoothly fit graphics of 640x480 (up to 100 hz) and 1024x768 (up to 75hz) resolutions into the visible region of the ntsc or pal screen. both horizontal and vertical sizes can be linearly adjusted. additional features include eight levels of flicker control using 5-line filter, zoom control and picture freeze. this highly integrated mix-signal chip, packaged in 24mm x 24mm 160-pin lqfp (low quad flat package), is powered by a single 5-volt power supply. power-down is achieved by using either hardware or software control. the enhanced features and superior quality make the AL128 very suitable for pc video to tv conversion in pc ready multimedia tv?s, scan converter boxes, vga add-on cards, web tvs, or network / laptop pcs.
AL128 april 2, 1999 5 4.0 pinout diagram AL128 blue5 121 blue6 120 blue4 122 md7 80 vdd 123 blue7 119 blue3 124 rgbout 1 blue2 125 gnd 118 blue1 126 vdd 79 blue0 127 green0 117 adgnd 128 pal 2 ab 129 green1 116 advdd 130 mwenl 78 advdd 131 green2 115 ag 132 inc 3 adgnd 133 green3 114 vrt 134 mwenh 77 vrb 135 vdd 113 adgnd 136 dec 4 ar 137 green4 112 advdd 138 memconf0 76 vdd 139 green5 111 ghsync 140 select 5 gvsync 141 green6 110 gnd 142 memconf1 75 gclk 143 green7 109 vdd 144 menu 6 ghsout 145 gnd 108 ghsdiv 146 gnd 74 gvsout 147 red0 107 /pwrdn 148 aden 7 /reset 149 red1 106 vdd 150 mwclk 73 tvclk 151 red2 105 clktype 152 vdd 8 xout2 153 red3 104 xin2 154 memtype 72 gnd 155 red4 103 intype1 156 test1 9 intype0 157 red5 102 xout1 158 mwrst 71 xin1 159 red6 101 gnd 160 sda 10 red7 100 vdd 70 vdd 99 i2caddr 11 mq0 98 mrrst 69 mq1 97 i2c 12 mq2 96 mrclk 68 mq3 95 scl 13 gnd 94 gnd 67 mq4 93 gnd 14 mq5 92 mren 66 mq6 91 test2 15 mq7 90 mq8 65 vdd 89 test3 16 md0 88 mq9 64 md1 87 test4 17 md2 86 mq10 63 md3 85 test5 18 gnd 84 mq11 62 md4 83 gnd 19 md5 82 vdd 61 md6 81 test6 20 mq12 60 test7 21 mq13 59 test8 22 mq14 58 test9 23 mq15 57 vdd 24 gnd 56 test10 25 md8 55 test11 26 md9 54 gvsout2 27 md10 53 ghsout2 28 md11 52 gnd 29 gnd 51 tvhsync 30 md12 50 tvvsync 31 md13 49 tvcsync 32 md14 48 test12 33 md15 47 davdd 34 vdd 46 vref 35 davdd 45 dagnd 36 davdd 44 ac/bout 37 comp 43 dagnd 38 rset 42 ay/gout 39 acmp/ rout 41 dagnd 40
AL128 april 2, 1999 6 5.0 pin definition and description total pin count: 160 pins symbol type pin description /pwrdn in ( cmosd) 148 power down enable (active low) /reset in ( cmosd) 149 reset (active low) ab in (0.7 v) 129 analog blue ac/bout out (1/0.7 v p-p) 37 analog chroma output or analog blue output acmp/rout out (1/0.7 v p-p) 41 analog composite output or analog red output aden in ( cmosd) 7 internal adc enable 0, internal adc disable 1, internal adc enable ag in (0.7 v) 132 analog green ar in (0.7 v) 137 analog red ay/gout out (1/0.7 v p-p) 39 analog luma output or analog green output blue<7:0> in ( cmosd) 119-122, 124- 127 graphic blue input data clktype in ( cmosd) 152 clock frequency 0 - 28.63636 mhz for ntsc, 35.46895 mhz for pal 1 - 14.31818 mhz for ntsc, 17.734475 mhz for pal comp in (0.1uf) 43 dac compensation pin, 0.1uf pull-up dec in ( cmossd) 4 decrement button gclk in (cmos) 143 graphic pixel clock ghsdiv out (cmos) 146 graphic pixel clock divide by m signal for external pll circuits. ghsout out (ttl) 145 graphic hsync output buffered from external vga hsync ghsout2 out (cmos) 28 no connection ghsync in ( cmosd) 140 graphic hsync green<7:0> in ( cmosd) 109-112, 114- 117 graphic green input data
AL128 april 2, 1999 7 gvsout out (ttl) 147 graphic vsync output buffered from external vga vsync gvsout2 out (cmos) 27 buffered graphic vsync output ii. gvsync in ( cmosd) 141 graphic vsync i2c in ( cmosd) 12 i 2 c/vsync programming select 0 - enable vga sync programming 1 - enable i 2 c programming i2caddr in ( cmosd) 11 i 2 c sub address 0 - write address = 88, read address = 89 1 - write address = 8c, read address = 8d inc in ( cmossd) 3 increment button intype<1:0> in ( cmosd) 156,157 graphic input type 00 - 24-bit rgb 01 - reserved 10 - feature connector 11 - vafc md<15:0> out (cmos) 47-50, 52-55, 80-83, 85-88 memory data to input of external field memory. memconf <1:0> in ( cmosd) 75,76 external memory configuration 00 ? reserved 01 ? one-field memory capture 10 ? two-field memory capture 11 ? reserved memtype in (cmosd) 72 memory type 0 - oki msm518221/222 1 ? averlogic al422 or nec m pd42280 menu in (cmossd) 6 menu button mq<15:0> in (cmosd) 57-60, 62-65, 90-93, 95-98 memory data from output of external field memory. mrclk out (cmos) 68 memory read clock mren out (cmos) 66 memory read enable mrrst out (cmos) 69 memory read reset mwclk out (cmos) 73 memory write clock mwenh out (cmos) 77 memory high byte write enable
AL128 april 2, 1999 8 mwenl out (cmos) 78 memory low byte write enable mwrst out (cmos) 71 memory write reset pal in ( cmosd) 2 ntsc/pal select 0 - ntsc 1 - pal red<7:0> in (cmosd) 100-107 graphic red input data rgbout in ( cmosd) 1 rgb/yc composite output select 0 - acmp, ay, ac 1 - r, g, b rset in 42 dac full scale current adjust, 82 ohm pull- down for s-video and composite output, 140 ohm pull-down for rgb output. scl in (cmossu) 13 i 2 c clock sda in/out (cmossu) 10 i 2 c data select in (cmossd) 5 select button test1~12 out (cmos) 9, 15-18, 20- 23, 25,26,33 unused pins for factory test purpose only tvcsync out (cmos) 32 tv composite sync tvhsync out (cmos) 30 tv horizontal sync tvvsync out (cmos) 31 tv vertical sync tvclk out (cmos) 151 clock output for graphic chip clock vrb in (0 v) 135 adc bottom voltage reference vref in (1.23 v) 35 dac voltage reference input vrt in 134 adc top voltage reference xin1/fin1 in (cmos) 159 crystal input/external clock input 1 for ntsc xin2/fin2 in (cmos) 154 crystal input/external clock input 2 for pal xout1 out (cmos) 158 crystal output 1 for ntsc xout2 out (cmos) 153 crystal output 2 for pal power and ground vdd x 13 5v 8, 24, 46, 61, 70, 79, 89, 99, 113, 123, 139, 144, 150 digital power
AL128 april 2, 1999 9 gnd x 14 14, 19, 29, 51, 56, 67, 74, 84, 94, 108, 118, 142, 155, 160 digital ground advdd x 3 5v 130,131,138 adc power adgnd x 3 128,133,136 adc ground davdd x 3 5v 34,44,45 dac power dagnd x 3 36,38,40 dac ground remarks: cmosd: cmos with internal pull-down cmossd: cmos with schmitt trigger and internal pull-down cmossu: cmos with schmitt trigger and internal pull-up pin list grouped by functionality symbol pin number graphic interface blue<7:0> 119-122, 124-127 green<7:0> 109-112, 114-117 red<7:0> 100-107 ghsync 140 gvsync 141 gclk 143 ghsdiv 146 ghsout 145 ghsout2 28 gvsout 147 gvsout2 27 field memory interface md<15:0> 47-50, 52-55, 80-83, 85-88 mq<15:0> 57-60, 62-65, 90-93, 95-98 mwenh 77
AL128 april 2, 1999 10 mwenl 78 mwrst 71 mren 66 mrrst 69 mwclk 73 mrclk 68 tv output acmp/rout 41 ay/gout 39 ac/bout 37 tvcsync 32 tvhsync 30 tvvsync 31 clocks xin1/fin1 159 xout1 158 xin2/fin2 154 xout2 153 tvclk 151 user interface scl 13 sda 10 menu 6 select 5 inc 3 dec 4 mode select pins rgbout 1 pal 2 intype<1:0> 156,157 memconf<1:0> 75,76 i2caddr 11
AL128 april 2, 1999 11 i2c 12 memtype 72 aden 7 clktype 152 /pwrdn 148 /reset 149 d/a converters comp 43 vref 35 rset 42 davdd x 3 34,44,45 dagnd x 3 36,38,40 a/d converters ar 137 ag 132 ab 129 vrt 134 vrb 135 advdd x 3 130,131,138 adgnd x 3 128,133,136 test pins test1~12 9, 15-18, 20-23, 25, 26, 33 digital power vdd x 13 8,24,46,61,70,79,89,99,113,123,139,144,150 gnd x 14 14,19,29,51,56,67,74,84,94,108,118,142,155,160
AL128 april 2, 1999 12 6.0 functional description the AL128 accepts either analog rgb or digital rgb data. the analog rgb data is digitized by three 50mhz 8-bit video a/d converters and is converted into 24-bit digital rgb data. for graphic controllers with standard or proprietary digital rgb output such as a high-color feature connector, vafc, or flat panel interface, the optional 24-bit digital rgb interface provides a solution for optimal video quality. the 24-bit digital rgb is passed to the digital processing unit of the chip. this dsp unit performs scan conversion operations and other digital signal processing such as flicker filtering, yuv filtering, scaling and color space conversion in the digital domain. the processed video data is sent to the digital tv encoder for converting into broadcast quality composite and s-video signals or original rgb format, which are in turn converted by three 9-bit d/a converters into analog outputs. functions can be controlled by dedicated hardware pins as well as software. the i 2 c interface provides full software programmability. the aforementioned hardware and software programmability also applies to the power-down feature. alternatively only four push buttons are required to control the major functions such as sharpness, pan, zoom, brightness, color bar output and position centering without the use of software or microcontroller. 6.1 input interface rgb data and horizontal and vertical sync signals of the vga controller are used as inputs. analog rgb data or 24-bit digital rgb data are both supported. the analog r, g, b signals are digitized with three built-in 8-bit a/d converters. the voltage swing of vga rgb signals is typically 0.7 volts. the vrt and vrb pins set the input voltage references of the a/d converters. when digital rgb data is used as the input, the internal a/d converters can be disabled by setting pin aden low, which may significantly reduce the power consumption. digital inputs for the AL128 can be either 24-bit rgb 888 or 16-bit rgb 565. rgb 565 can in turn be in vafc or feature connector format. the intype pins of the AL128 have to be set correctly to match the different applications. intype <1:0> pin 156, pin 157 digital graphic input type 0 0 24-bit rgb 0 1 reserved 1 0 feature connector (rgb565) 1 1 vafc (rgb565)
AL128 april 2, 1999 13 6.1.1 24-bit rgb the digital 24-bit rgb can be pin-to-pin wired to red<7:0>, green<7:0> and blue<7:0> of the AL128. 6.1.2 vafc the vafc format (16-bit, rgb565, in 64k high color) carries red signals in d15~d11, green signals in d10~d5, and blue signals in d4~d0. there are two ways to implement vafc interface. the first way is to set intype as 11 to accept vafc format, then input the 16-bit rgb565 (64k high color) to green<7:0> and blue<7:0> of the AL128 as follows: the other way is to keep intype setting as 00 to accept 24-bit rgb888, but connect the inputs to the higher bits of red<7:0>, green<7:0> and blue<7:0> of the AL128 as follows. the unused pins can be grounded. d15 red 7 d14 red 6 d13 red 5 d12 red 4 d11 red 3 d10 green 7 d9 d8 d7 d6 d5 d4 blue 7 d3 d2 d1 d0 green 6 green 5 green 4 green 3 green 2 blue 6 blue 5 blue 4 blue 3 d15 d14 d13 d12 d11 d10 d9 d8 green 7 green 6 green 5 green 4 green 3 green 2 green 1 green 0 d7 d6 d5 d4 blue 7 d3 d2 d1 d0 blue 6 blue 5 blue 4 blue 3 blue 2 blue 1 blue 0
AL128 april 2, 1999 14 6.1.3 feature connector the definition of the data bits of the feature connector is same as that of the vafc, i.e., d15~d11 represent red signals. d10~d5 green signals, and d4~d0 blue signals. however, since the feature connector uses 8-bit interface, the two bytes of data must be received within one pixel/graphic clock (gclk). the solution is: one byte at the rising edge and one byte at the falling edge of gclk as follows: the eight-bit data is wired to blue<7:0> of the AL128 as follows: 6.1.4 sampling (pixel) clock the sampling clock for the rgb data can come directly from the graphic pixel clock when this is available. for external box applications where the graphic pixel clock is not available, the clock is recovered from the vga horizontal sync with an external pll clock chip such as ics av9173. the phase reference signal of the pll clock chip is generated by the divide-by-m circuitry of the AL128. the AL128 automatically sets the m divider value, which determines the sampling frequency for the a/d converter according to the detected resolution of the incoming graphic data. gclk data d7~d0 d15~d8 d7~d0 d7~d0 d15~d8 d15 d14 d13 d12 d11 d10 d9 d8 blue 7 blue 6 blue 5 blue 4 blue 3 d7 d6 d5 d4 d3 d2 d1 d0 blue 2 blue 1 blue 0
AL128 april 2, 1999 15 6.2 hardware and software control modes the AL128 is powered up to a default state depending on the hardware mode-setting pins. eight of these hardware configuration pins are disabled by setting softconfig (bit 4 of register 03h) to one, and configurations are decided by the values of register 0x02, programmable by software. by default, AL128 major functions can be controlled by on screen display menu (osdm) push buttons. the registers related to these functions have no effect on those on screen display menu functions unless disbutton (bit 3 of register 03h) is set to one. when this bit is set to one, the external osdm push buttons are deactivated and those functions are controlled by software programming. the following table lists the functions that can be controlled by either push buttons or software programming, and their corresponding registers. function register name register index sharpness vfltmode 33h<2:0> zoom zoom zoomen 20h<1:0> 20h<7> pan ginhstartdlt ginvstartdlt ginhstzoomdlt ginvstzoomdlt 21h<7:0> 22h<7:0> 2bh<6:0> 2ch<6:0> underscan softudscan 33h<6> position tvhstartdlt tvvstartdlt 52h<7:0> 51h<7:0> brightness tvbright 50h<4:3> color bar colorbar 50h<1> details about the programming can be found in the register definition section. 6.3 video timing although the AL128 is designed to be plug-&-play, it is programmable to meet special requirements. this is especially advantageous when al422 is used as field memory since larger memory capacity means higher sampling resolution. horizontal capture and display timing is as follows:
AL128 april 2, 1999 16 vertical capture and display timing is as follows: h total (reg # 28h) hsync h pan delta (reg # 21h), (reg # 2bh for zoom) h capture size (reg # 23h) default capture start h-display delta (reg # 52h) horizontal display size (horizontal active region shown on tv) default horizontal display start * scaled up ratio defined in reg # 27h AL128-16 timing_horizontal vga input tv output tvhsync
AL128 april 2, 1999 17 details about register programming can be found in the register definition section. typical values of the parameters for using AL128 with al422 can be found in the AL128 application notes supplement. 6.4 supported resolutions the resolutions that are automatically supported without any software are 640x400, 640x480 and 800x600. other resolutions, such as 1024x768 full screen, are also supported through software programming. scan rates up to 100 hz are supported for 640x480 resolution, up to 85 hz for 800x600 resolution, and up to 75 hz for 1024x768 resolution. v-total (reg # 43h) vsync source vertical size (reg# 24h) v-pan delta (reg #22h), (reg #2ch for zoom) down-sample vertical size (reg #25h) v-display delta (reg #51h) default v-capture start (see h/w table) * ratio defined in reg # 26h vga input tv output AL128-17 timing_vertical tvvsync default vertical display start (see h/w table)
AL128 april 2, 1999 18 6.5 flicker filter the AL128 chip performs 5 line flicker filtering to reduce the flicker due to interlaced display of high contrast lines. eight levels of flicker reduction, as well as sharpness adjustment, are provided to control the picture quality. proprietary dynamic filtering ( smartfilter ? ) is applied to retain the original pc video resolution and sharpness while removing the flickering effect. the hardware intelligently detects which parts of the screen are natural picture and which are text whose clarity needs to be retained. one out of 45 different filters is selected and applied dynamically for each single pixel based on the statistics of its surrounding pixels. the criteria of which filter to choose from is based on a model derived from the ensemble of psychophysical experiments based on human eye responses to the flicker of different picture types. 6.6 overscan/underscan control televisions normally overscan, meaning that the border of the picture is outside the visible area of the tv screen. to program the AL128 from overscan to underscan, reduce the horizontal display width and vertical display height, and increase the h-display delta and v-display delta. for underscan to overscan, reverse the process. the capture-related registers may need to be programmed for optimization. the AL128 linearly scales the input picture into the visible part of a tv?s screen. digital filtering techniques are applied to remove the scaling artifacts. 6.7 pan and position control the panning feature selects the portion of the graphic picture to be displayed on the tv screen. when in zoom mode, the visible screen can be progressively panned to any area of the virtual screen. to pan the display, change the values of h-pan delta (reg. #21h, #26h) and v-pan delta (reg. #22h, 2ch). to pan in zoom mode, #2bh and #2ch may also need to be programmed. position control is used to center the video on the tv screen. to position the display, change the values of h-display delta (reg. #52h) and v-display delta (reg. #51h). 6.8 zoom feature AL128 performs 2x zoom in both horizontal and vertical directions. this can be used with panning, or activated by jumping to any given quadrant via use of the push buttons or software.
AL128 april 2, 1999 19 to zoom, use register #20h to enable it, and then use #2bh and #2ch to position it. 6.9 frame buffer management only one half mbytes of field memory are needed to achieve 24-bit video quality and full resolution scan conversion for either ntsc or pal. field memory supported is averlogic al422, nec m pd42280 and oki msm518221/222. with less memory than other solutions on the market, high resolution data is processed and stored by using a complex and proprietary frame buffer management system. there is no compromise with video quality by using either compression or sub-sampling algorithms. special care is taken in the design so that there is no tearing effect (feathered edge) when playing back moving video sequences such as mpeg i or mpeg ii. to take advantage of the high capacity of the al422, please review the AL128 application notes supplement for details. 6.10 digital video encoder the digital video encoder inputs the digital color-space and scan-rate converted video data and output broadcast quality ntsc and pal signals. the color sub-carrier is generated by a four times over-sampling clock, which greatly simplifies external analog smoothing filter design. eight times over-sampling mode is also available by software control. the modulated digital signals are converted to analog levels by three 9-bit d/a converters. composite and s-video signals are output simultaneously. interlaced rgb output can also be provided. 6.11 push button interface/osd the push button interface is used with the on-screen-display menu. there are four buttons: menu, select, increment and decrement. functions controlled by these push buttons are pan, zoom, position centering, brightness, underscan, color bar and sharpness. the AL128 evb provides a user-friendly on-screen control with four push buttons, [menu], [select], [<] and [>], for end users to control the major functions of the AL128. there are eight on- screen control functions, which are: sharpness panning p ositioning color bar zoom over/underscan brightness home settings
AL128 april 2, 1999 20 to pop up the on screen menu, press the [menu] button. to select a control function, use the [<] or [>] button to scroll to it, then press the [select] button. after selecting a control function, use the [select], [<] or [>] button to adjust the control effects. to exit the on screen menu, press [menu] again. 6.12 memory control timing the AL128 uses fifo frame buffers such as the al422 for scan rate conversion. the input analog rgb signals are digitized at the regenerated gclk speed. the captured and filtered digital data is written to the fifo?s at a slower speed by using mwenh and mwenl to reduce the bandwidth while the mwck is maintained at the same speed as gclk (with a slight phase difference). the enable duty cycle of the mwenh and the mwenl is programmable by controlling register #25h, as long as the captured data volume does not exceed the fifo capacity. the mwenh controls luma data write enable; the mwenl controls chroma data write enable. after the whole frame data is written, the wrrst is applied right before the next input frame is to be captured to reset the write pointer back to zero. the following drawing shows the graphic sync signals and fifo control write timing:
AL128 april 2, 1999 21 vsync mwrst sync back porch front porch active lines vsync hsync mwrst mwenh mwenl AL128-26 fifo control vga timing hsync mwrst mwenh mwenl active pixels back porch front porch sync hsync mwenl (chroma) mwenh (luma) ghsdiv (for pll) 32 cycles gclk
AL128 april 2, 1999 22 the read clock rclk is either 14.318mhz for ntsc or 17.734mhz for pal. not every single pixel of input data is read so that the bandwidth may fit the lower tv resolution, and this is controlled by various enable duty cycles of the ren. pal has a higher enable duty cycle than ntsc because of its higher resolution. mrrst is applied right before the next valid output field to reset the read pointer back to zero. the following drawing shows the tv sync signals and fifo control read timing: rck ren front porch back porch ren tvhsync AL128-27 fifo control tv timing mrrst sync back porch front porch active lines tvvsync tvhsync tvvsync mrrst cvbs
AL128 april 2, 1999 23 6.13 i 2 c programming the al100/110/128 i 2 c programming interface is slightly different from the philips standard (same write cycles but different read cycles). the i 2 c interface consists of the scl (clock) and sda (data) signals. data can be written to or read from the al100/110/128. for both read and write, each byte is transferred msb first, and the sda data bit is valid when the scl is pulled high. the read/write command format is as follows: write :
read :
following are the details: < s >: start signal scl sda high high high low the start signal is high to low transition on the sda line when scl is high. < write sa >: write slave address: 88h or 8ch : read slave address: 89h or 8dh < register index >: value of the al100/110/128 register index. < a >: acknowledge stage the acknowledge-related clock pulse is generated by the host (master). the host releases the sda line (high) for the al100/110/128 (slave) to pull down the sda line during the acknowledge clock pulse. < na >: not acknowledge stage the acknowledge-related clock pulse is generated by the host (master). the host releases the sda line scl sda sda scl sda scl scl sda scl data bit [1] or na data bit [0] or a start bit [s] stop bit [p] not significant al250-15 i2c drawing
AL128 april 2, 1999 24 (high) during the acknowledge clock pulse, but the al100/110/128 does not pull it down during this stage. < data >: data byte write to or read from the register index. in read operation, the host must release the sda line (high) before the first clock pulse is transmitted to the al100/110/128. < p >: stop signal scl sda high low high high the stop signal is low to high transition on the sda line when scl is high. suppose data f0h is to be written to register 0fh using write slave address 88h, the timing is as follows (same as the philips standard): suppose data is to be read from register 55h using read slave address 89h , the timing is as follows: start slave addr = 88h ack ack ack stop index = 0fh data = f0h sda scl AL128-24 i2c write timing slave addr = 89h ack nack stop data read cycle sda scl
AL128 april 2, 1999 25 in comparison, reading data from register 55h using slave address 59h with philips standard would be as follows: start ack ack index = 55h read slave addr = 59h sda scl al250-25 i2c read timing nack data read cycle stop
AL128 26 7.0 electrical characteristics parameter min unit vdd +3.8 +5.5 tamb ambient operating temperature +70 parameter test conditions max unit i dd supply current 230 350 ma p power consumption 875 1925 mw v ih hi-level input voltage 0.7vdd vdd+0.5 v v il lo-level input voltage -0.5 +0.8 v v oh hi-level output voltage 2.4 vdd v v ol lo-level output voltage - 0.5 v i li input leakage current - 1 m a c i input pin capacitance - 8 pf t su input data set-up time 10 - ns t hd input data hold time 3 - ns c l digital output load cap. 15 50 pf t oh output hold time c l = 15pf 5 - ns t pd propagation delay c l = 40pf - 15 ns t r output rise time vi = 0.6 to 2.6v 3 7 ns t f output fall time vi = 2.6 to 0.6v 3 7 ns
AL128 april 2, 1999 27 8.0 AL128 register definition 8.1 index of the control registers register index function configuration companyid 00h company id number revision 01h revision number boardconfig 02h board configuration general 03h general control version 04h chip family number push button interface softbutton 18h software button i buttonstatus 19h software button ii graphic input graphctrl 20h graphic control ginhstartdlt 21h delta of horizontal start ginvstartdlt 22h delta of vertical start gincaphsize 23h horizontal capture size ginysize 24h source picture vertical size capvsize 25h destination picture vertical size capvratio 26h vertical scale ratio dsphratio 27h horizontal scale ratio plldivider 28h pll clock divider ginhstzoomdlt 2bh delta of horizontal start in zoom mode ginvstzoomdlt 2ch delta of vertical start in zoom mode graphdp 33h graphic data processing control 40h reserved (for assisting memory control) read only status registers hwconfig 41h hardware configuration status ginhtotal 42h detected horizontal total
AL128 april 2, 1999 28 ginvtotal 43h detected vertical total scanrate 44h detected scan rate tvstatus 45h vertical position status encoder encoderctrl 50h encoder control tvvstartdlt 51h delta of vertical display start tvhstartdlt 52h delta of horizontal display start capinv 53h capture control miscellaneous mcapvratio 71h m of vertical capture ratio value: n/m ncapvratio 72h n of vertical capture ratio value: n/m chromabypass 73h chroma filter bypass control 8.2 control register description 00h: company id (r) [companyid] companyid <7:0> company id (0x46) 01h: revision (r) [revision] revision <7:0> 00000001, revision id numbers 02h: board configuration (r/w) [boardconfig] intype <1:0> graphic input data format 00 digital rgb 888 01 reserved 10 feature connector 11 vafc memconf <3:2> external memory configuration 00 no external memory used 01 one-field memory capture only one field of video data is stored in the field memory. this proprietary design increases the resolution with limited 512kb memory (thus bringing better output quality), but does not work when the input refresh rate is
AL128 april 2, 1999 29 less than 66hz for ntsc or 55hz for pal, or when freeze control is used. 10 two-field memory capture both odd and even fields of video data are stored in the field memory. when the al422 is used as the field memory, there is enough capacity at all times so this mode is suggested for programming simplicity. 11 reserved memtype <4> memory type 0 oki field memory 1 nec f ield memory pal <5> pal/ntsc select 0 ntsc 1 pal f4sc <6> 0 use 8 times sc sampling clock as tv clock 1 use 4 times sc sampling clock as tv clock rgbout <7> 0 composite and s-video output 1 rgb output settings of this register are enabled only when software programming is turned on by writing 18h to reg.#03h. 03h: general (r/w) [general] pwrdown <0> power down the chip if set to 1. <2:1> reserved disbutton <3> disable touch button function; use i2c/vsync interface to program the chip. this bit has to be turned on to enable all the functions marked as ** xxx **. softconfig <4> enable configuration defined by software configuration registers 0x02. reserved <7:5> to use software programming properly, read the value of reg.#41h (hardware configuration) and write it to reg.#02h. then write value 18h to reg.#03h. 04h: chip family (r) [version] family <7:0> 00000000, al100 series push-button interface 18h: push button value (r/w): [softbutton]
AL128 april 2, 1999 30 <0> reserved <1> reserved <3:2> reserved valueptr <7:4> number of on-screen-display white rectangle bar, to indicate the level of strength. works only when reg.#19h <1> is turned on. 19h: push button status (r/w): [buttonstatus] dspmenu <0> enable display of on-screen-display menu icons dspvalue <1> enable display of on-screen-display function icons dspleftr <2> enable display of on-screen-display left-right icon dspupdn <3> enable display of on-screen-display up-down icon funcptr <6:4> current function icon selected and highlighted. 00 0: sharpness function icon 001: zoom function icon 010: pan function icon 011: underscan/overscan function icon 100: position function icon 101: brightness function icon 110: color bar function icon 111: home function icon <7> reserv ed graphic input block 20h: graphics control register (r/w) [graphctrl] zoom <1:0> zoomed quadrant ** zoom ** 00 zoom quadrant 0 01 zoom quadrant 1 10 zoom quadrant 2 11 zoom quadrant 3 meaningful only when zoomen = 1. it is recommended not to set these bits when s/w mode is enabled. instead, use reg#2bh and reg#2ch to control the zoomed video visible area. vga555 <2> vga vafc/feature connector 555/565 format select 0: 565 format 1: 555 format
AL128 april 2, 1999 31 <3> reserved <4> reserved <5> reserved <6> reserved zoomen <7> zoom enable ** zoom ** set to 0 when in basic mode. 21h: delta of horizontal start (r/w) [ginhstartdlt] ginhstartdlt <7:0> delta of default horizontal capture start position. ( unit: 8 pixels) ** x pan ** this register does not apply to zoom mode. the actual horizontal capture start position is defined as: ( default horizontal capture start position) + ( ginhstartdlt * 8). the value of ginhstartdlt is signed, and its value is between ?128 and 127. please refer to section 8.3, AL128 plug & play hardware table for the default horizontal capture start positions. 22h: delta of vertical start (r/w) [ginvstartdlt] ginvstartdlt <7:0> bit-9 to bit-2 of ginvstartdlt; bit 1,0 are defined in register 0x26. (unit: one line) ** y pan ** this register does not apply to zoom mode. the actual vertical capture start position is defined as: ( default vertical capture start position) + ( ginvstartdlt * 4). the value of ginvstartdlt is signed, and its value is between ?128 and 127. please refer section 8.3, AL128 plug & play hardware table for the default vertical capture start positions. 23h: horizontal capture size (r/w) [gincaphsize] gincaphsize <6:0> horizontal capture size (unit: 16 pixels) softcaphsize <7> override default h capture size value and use gincaphsize if set to 1. this register defines the number of pixels of each valid horizontal line, which length is defined by reg#22h (zoom off) or reg#2ch (zoom on). only the active horizontal lines are captured, and the range is defined by reg#24h and reg#25h. the actual horizontal capture size is defined as: gincaphsize * 16. the starting capture position is defined by reg#21h (zoom off) or reg#2bh (zoom on). the destination total displayed active pixels is defined as: gincaphsize * 16 * (scale-up ratio defined in reg#27h) please also refer to section 6.3 video timing for better understanding.
AL128 april 2, 1999 32 make sure that: ( gincaphsize * 16) <= 800(al100/128 built-in line buffer size) ( gincaphsize * 16) <= (reg#28h<6:0> * 16) for one-field memory configuration, the value of ( gincaphsize * 16) * (reg#25h<6:0> * 8) * 2 must be less or equal to the total field memory size on board. for two-field memory configuration, the value of ( gincaphsize * 16) * (reg#25h<6:0> * 8) * 2 * 2 must be less or equal to the total field memory size on board. 24h: source vertical size (r/w) [ginvsize] ginvsize <6:0> vertical size of graphic input (unit: 8 lines) softvsize <7> override hardware detected v size value and use ginvsize if set to 1. this register defines the total number of input lines scanned, which starting position is defined by reg#22h (zoom off) or reg#2bh (zoom on). the scanned input lines are scaled (down-sampled), filtered and captured into field memory. the destination down-sampled size is defined in reg#25h. the actual vertical source size is defined as: ginvsize * 8. the starting position to scan input lines is defined by reg#22h (zoom off) or reg#2bh (zoom on). see reg#26h for more description. please also refer to section 6.3 video timing for better understanding 25h: down-sampled vertical size (destination) [capvsize] (r/w) capvsize <6:0> (unit: 8 lines) capvsizeen <7> enable software vertical size this register defines the total number of scaled (down-sampled) and filtered video lines captured into the field memory. the actual number is defined as: capvsize * 8. for one-field memory configuration, the value of (reg#23h<6:0> * 16) * ( capvsize * 8) * 2 must be less or equal to the total field memory size on board. for two-field memory configuration, the value of (reg#23h<6:0> * 16) * ( capvsize * 8) * 2 * 2 must be less or equal to the total field memory size on board. see reg. #26h for more description please also refer to section 6.3 video timing for better understanding 26h: y downscale ratio [capvratio] (r/w) capvratio <3:0> 0000 no line drop 0001 drop 3 lines out of 10 lines xxxx (from 0010 to 1110): drop one line for every xxxx+1 lines 1111 vertical scale ratio defined as n/m
AL128 april 2, 1999 33 n is defined at reg.#72h<5:0> m is defined at reg.#71h<5:0> capvratioen <4> 0: hardware default vertical scale ratio used for vertical scaling. 1: software vertical down-scale ratio capvratio used. <5> reserved ginvstartdlt <7:6> bit 1,0 of 10-bit ginvstartdlt. used with reg 0x22 the relationship between registers #24h, #25h and #26h is that reg. #25h<6:0> approximately equals to reg. #24h<6:0> * (vertical scale ratio define in reg. #26h) please also refer to section 6.3 video timing for better understanding 27h: horizon tal scale ratio [dsphratio] (r/w) dsphratio <5:0> software horizontal scale ratio. the value is ((hsrc/hdst) x 256 ? 128) / 2 hsrc is horizontal capture size defined in reg. #23h hdst is horizontal display active size. the default overscan hds t for ntsc is 752; pal is 954 the default underscan hdst for ntsc is 656; pal is 800 the pixel total for 910x525 for ntsc, 1126x615 for pal the suggested hdst in zoom mode is 736~836 (ntsc) and 800~1203 (pal). please review the s.5.2 and s.5.3 sections of the AL128 application notes (and find the dsph value in different input modes) for details hscaleen <6> 0: use default hardware horizontal scale ratio. 1: use dsphratio and softnoscale to control horizontal scale ratio. softnoscale <7> turned on when horizontal scaling ratio is 1:1. don?t care if bit<6> = 0. the al100 series perform horizontal up-scaling only. for down-scaling, reduce capture size instead by programming reg.#28h. the destination total displayed active pixels is defined as: reg#23h<6:0> * 16 * (hdst/hsrc) please also refer to section 6.3 video timing for better understanding. 28h: graphic clock pll divider (r/w) [plldivider] plldiv <6:0> pll divider number (unit: 16 pixels) plldiven <7> pll divide number enable 0 use default hardware divider value. 1 use plldiv registers for the pll divider number.
AL128 april 2, 1999 34 this register defines the horizontal total sampled pixels between 2 continuous input horizontal sync. the actual number is defined as: plldiv * 16 make sure that the v alue of (graphic clock pll divider) * (detected vertical total) * (detected scan rate) does not exceed the maximum speed of the field memory used, e.g., plldiv * 16 * ginvtotal * 4 * vgarr <= 56mhz for al422 plldiv , ginvtotal and vgarr are defined by registers 28h, 43h and 44h respectively. 2bh: delta of horizontal start in zoom mode (r/w) [ginhstzoomdlt] ginhstzoomdlt <6:0> (unit: 8 pixels) ** x pan (in zoom mode) ** <7> reserved this does not apply to non-zoom mode. the actual horizontal capture start position is defined as: ( default horizontal capture start position) + ( ginhstzoomdlt * 8). the value of ginhstzoomdlt is signed, and its range is between ?64 and 63. please refer to section 8.3, AL128 plug & play hardware table for the default horizontal capture start positions. 2ch: delta of vertical start in zoom mode (r/w) [ginvstzoomdlt] ginvstzoomdlt <6:0> (unit: 4 lines) ** y pan (in zoom mode) ** <7> reserved this does not apply to non-zoom mode. the actual vertical capture start position is defined as: ( default vertical capture start position) + ( ginvstzoomdlt * 4). the value of ginvstzoomdlt is signed, and its range is between -64 and 63. please refer to section 8.3, AL128 plug & play hardware table for the default vertical capture start positions. 33h: graphic data processing (r/w) [graphdp] vfltmode <2:0> vertical flicker filter mode select ** filter modes ** udscanx <3> h direction only underscan this only reply to h/w default mode. for s/w mode, please use reg#28h and reg#23h to control the horizontal sampling and set this bit to 0 <4> reserved <5> reserved softudscan <6> 1: underscan ; 0: overscan. to disable the hardware default settings of the underscan mode, program this bit as 0. for s/w control, use reg#28h and reg#23h to control the horizontal sampling and set this bit to 0 <7> reserved
AL128 april 2, 1999 35 40h: reserved (r/w) reserved for assisting memory control, works only when memconf is set as two-field memory capture. to be turned on only when there is memory i/o timing conflict. suggested value is 81h for 1024x768 input / overcan pal output, and 00h for other modes. status read only registers 41h: hardware configuration (r only) [hwconfig] intype <1:0> graphic input data format 00 digital rgb 888 01 reserved 10 feature connector 11 vafc memconf <3:2> external memory configuration 00 no external memory used 01 one-field memory capture see reg#02h for more information 10 two-field memory capture see reg#02h for more information 11 reserved memtype <4> memory type 0 oki field memory 1 averlogic al422, nec or panasonic field memory pal <5> pal/ntsc select 0 ntsc 1 pal f4sc <6> 0 use 8 times sc sampling clock as tv clock 1 use 4 times sc sampling clock as tv clock rgbout <7> 0 composite and s-video outpu t 1 rgb output 42h: detected horizontal total (r only) [ginhtotal] ginhtotal <7:0> detected horizontal total (unit: 8 pixels) for input resolution of 640x480 or 800x600, the value of ( ginhtotal * 8) equals to (reg#28h<6:0> * 16). for higher input resolution, plldiv needs to be lower than the detected horizontal total so as not to exceed the speed limit of the field memory.
AL128 april 2, 1999 36 43h: detected vertical total (r only) [ginvtotal] ginvtotal <7:0> detected vertical total (unit: 4 lines) this value can al so be used to determine the input resolution: detected vertical total estimated input resolution <480 720 x 400 (dos mode) 481~600 640 x 480 (vga) 601~768 800 x 600 (svga) >769 1024 x 768 (xga) 44h: detected scan rate (r only) [scanrate] scanperiod <6:0> total number of tv lines counted during an input vga frame period, in unit of 4 lines. ginvsync <7> 1 if graphic vsync is active to determine the vga refresh rate ( vgarr): for ntsc: vgarr = (525 / (reg.#44h<6:0>)) * 59.94 / 8 for pal: vgarr = (625 / (reg.#44h<6:0>)) * 50 / 8 45h: vertical postion status (r only) [tvstatus] gindata <2:0> green0, blue1, blue0 pins , reserved as input ports when these hardware pins are not used for digital input. i2cp <3> i2c pin i2cp <4> i2c address select pin tvblank <5> tv blanking signal tvfield <6> odd/even field 0 even field 1 odd field tvvsync <7> 1 if tv vsync is active encoder output block 50h: encoder control: (r/w) [encoderctrl] reserved <0> colorbar <1> color bar enable ** color bar ** bw <2> make tv output black and white tvbright <4:3> tv brightness control ** brightness ** filter2 <5> turned on only for tv without comb filter
AL128 april 2, 1999 37 <7:6> reserved 51h: delta of vertical display start line (r/w) [tvvstartdlt] tvvstartdlt <7:0> delta of vertical start line no. (unit: 4 lines) ** y position ** the actual vertical display start position is defined as: ( default vertical display start position) + ( tvvstartdlt * 4). the value of tvvstartdlt is signed, and its range is between ?128 and 127. please refer to section 8.3, AL128 plug & play hardware table for the default vertical display start positions. 52h: delta of horizontal display start position (r/w) [tvhstartdlt] tvhstartdlt <7:0> delta of horizontal display start pixel no. (unit: 8 pixels) ** x position ** the actual horizontal display start position is defined as: ( default horizontal displaye start position) + ( tvhstartdlt * 8). the value of tvhstartdlt is signed, and its value is between ?128 and 127. please refer to section 8.3, AL128 plug & play hardware table for the default horizontal display start positions. 53h: overrun test register (r/w) [capinv] freeze <0> freeze the picture , use only two-field memory configuration mode. <7:1> reserved miscellaneous control block 70h: reserved (r/w) when <7:5> = 101, pin test6 (the internal luma<3>) works as hde signal (horizontal data enable input), pin test7 (the internal luma<2>) works as vde signal (vertical data enable output). 71h: vertical capture ratio m control: (r/w) [mcapvratio] m <5:0> 72h: vertical capture ratio m control: (r/w) [mcapvratio] n <5:0>
AL128 april 2, 1999 38 73h: chroma filter bypass control: (r/w) [chromabypass] nocfilt <3> chroma filter bypass control; enhance s-video color resolution only when composite output is not used. 0 disabled 1 enabled uvflip <2> flip uv 8.3 AL128 plug & play hardware table ntsc pal underscan overscan underscan overscan 640x400 (dos) caph: 648 capv: 404->404 caphst: 136 capvst: 28 dsph: 648->648 dspv: 404 dsphst: 176 dspvst: 74 hpll: 800 same as ntsc underscan defined left caph: 648 capv: 404->404 caphst: 136 capvst: 28 dsph: 648->648 dspv: 404 dsphst: 288 dspvst: 136 hpll: 800 same as pal underscan defined left 640x480 reg.#02h<3> = 0 or vga refresh rate: ntsc: >= 66 hz pal: >= 56 hz caph: 656 capv: 480->420 caphst: 160 capvst: 20 dsph: 656->656 dspv: 420 dsphst: 152 dspvst: 68 hpll: 832 caph: 656 capv: 480->480 caphst: 160 capvst: 20 dsph: 656->752 dspv: 480 dsphst: 136 dspvst: 32 hpll: 832 caph: 656 capv: 480->480 caphst: 160 capvst: 20 dsph: 656->656 dspv: 480 dsphst: 288 dspvst: 96 hpll: 832 same as pal underscan defined left 640x480 reg.#02h<3> = 1 or vga refresh rate: ntsc: < 66 hz pal: < 56 hz caph: 512 capv: 480->420 caphst: 120 capvst: 20 dsph: 512->656 dspv: 420 dsphst: 152 dspvst: 68 hpll: 640 caph: 512 capv: 480->480 caphst: 120 capvst: 20 dsph: 512->752 dspv: 480 dsphst: 136 dspvst: 32 hpll: 640 caph: 512 capv: 480->480 caphst: 120 capvst: 20 dsph: 512->656 dspv: 480 dsphst: 288 dspvst: 96 hpll: 640 same as pal underscan defined left
AL128 april 2, 1999 39 800x600 reg.#02h<3> = 0 or vga refresh rate: ntsc: >= 66 hz pal: >= 56 hz caph: 656 capv: 600->420 caphst: 160 capvst: 28 dsph: 656->656 dspv: 420 dsphst: 152 dspvst: 68 hpll: 832 caph: 656 capv: 600->480 caphst: 160 capvst: 28 dsph: 656->752 dspv: 480 dsphst: 136 dspvst: 32 hpll: 832 caph: 800 capv: 600->500 caphst: 200 capvst: 28 dsph: 800->800 dspv: 500 dsphst: 224 dspvst: 84 hpll: 1024 caph: 800 capv: 576->576 caphst: 200 capvst: 28 dsph: 800->928 dspv: 576 dsphst: 152 dspvst: 24 hpll: 1024 800x600 reg.#02h<3> = 1 or vga refresh rate: ntsc: < 66 hz pal: < 56 hz caph: 512 capv: 600->420 caphst: 120 capvst: 28 dsph: 512->656 dspv: 420 dsphst: 152 dspvst: 68 hpll: 640 caph: 512 capv: 600->480 caphst: 120 capvst: 28 dsph: 512->752 dspv: 480 dsphst: 136 dspvst: 32 hpll: 640 caph: 656 capv: 600->500 caphst: 160 capvst: 28 dsph: 656->800 dspv: 500 dsphst: 224 dspvst: 84 hpll: 832 caph: 656 capv: 576->576 caphst: 160 capvst: 28 dsph: 656->928 dspv: 576 dsphst: 152 dspvst: 24 hpll: 832 remarks: caph : horizontal capture width capv : vertical capture height caphst : horizontal capture start capvst : vertical capture start dsph : horizontal display width dspv : vertical display height dsphst : horizontal display start dspvst : vertical display start hpll : horizontal total -> : scaled to
AL128 april 2, 1999 40 9.0 board design and layout considerations the AL128 is a highly integrated mixed-signal ic. it contains both precision analog and high speed digital circuitry. special care needs to be taken in order to maintain the best video quality. noise coupling from digital circuits to analog circuits may result in poor video quality. therefore, the layout should be optimized for lowest noise on the power and ground planes by shielding the digital circuitry and providing good decoupling. it is recommended to place the AL128 chip close to the graphic and video input/output connectors. 9.1 grounding analog and digital circuits are separated within the AL128 chip. to minimize system noise and prevent digital system noise from entering the analog portion, a common ground plane for all devices, including the AL128, is recommended. all the connections to the ground plane should have very short lead. the ground plane should be solid, not cross-hatched. 9.2 power planes the analog portion of the AL128 and any associated analog circuitry should have their own power plane, referred to as the analog power plane (avdd). the analog power plane should be connected to the digital power plane (dvdd) at a single point through a low resistance ferrite bead. the d/a conversion circuitry within the AL128 uses the dvdd power. the digital power plane should provide power to all digital logic on the pc board, and the analog power plane should provide power to all of the AL128 analog power pins and relevant analog circuitry. the digital power plane should not be placed under the AL128 chip, the voltage references or other analog circuitry. capacitive coupling of digital power supply noise from this layer to the AL128 and its related analog circuitry can degrade video output quality. 9.3 power supply decoupling power supply connection pins should be individually decoupled. for best results, use 0.1 m f ceramic chip capacitors. lead lengths should be minimized. the power pins should be connected to the bypass capacitors before being connected to the power planes. 22 m f capacitors should also be used between the AL128 power planes and the ground planes to control low-frequency power ripple. 9.4 digital signal and clock interconnect digital signals to the AL128 should be isolated as much as possible from the analog outputs and other analog circuitry. also, these signals should not overlap the analog power plane. if this is not possible, coupling can be minimized by routing the digital signal at a 90 degree angle across the analog signals.
AL128 april 2, 1999 41 the high frequency clock reference or crystal should be handled carefully. jitter and noise on the clock will degrade the video performance. keep the clock paths to the AL128 as short as possible to reduce noise pickup. locate phase locked loop components close to the relevant AL128 pins. isolate these components from noise. 9.5 analog signal interconnect the AL128 should be located closely to the output connectors to minimize noise and reflections. keep the critical analog traces as short and wide as possible. high frequency digital signals, especially pixel clocks and data signals should never overlap any of the analog signal circuitry and should be kept as far away as possible. the AL128 should have no inputs left floating. each of the unused analog input pins should be connected to gnd. all of the digital input pins are internally pulled down. the analog output traces should also not cross the AL128 and vdd power planes to maximize high- frequency power supply rejection. 9.6 component placement the suggested component placement is as follows: remarks: 1. pll crystal/oscillator circuits should be placed at the lower left corner and close to AL128 to avoid noise interference. analog power pll xtal rgb input AL128 al422 al422 AL128-15 layout considerations tv output (separated and shielded)
AL128 april 2, 1999 42 2. vga input and tv output are both analog signals so should be away from high frequency digital signals as much as possible. use thicker connection such as 20 or 30 mil wires. output signals should not be too far away from the output connectors and should be shielded properly. shielding in between the output signals is recommended as well. 3. analog power should be arranged at the upper left corner of the AL128 only (the output circuits including dac?s share the same power plane with digital power plane so do not need to use analog power). keep the analog power separated and clean to avoid noise interference. 10.0 mechanical drawing the AL128 is fabricated using cmos process and packaged in a low profile 24mm x 24mm 160-pin lqfp package. this package type is perfect for pcmcia or laptop computer applications. optional 28mm x 28mm pqfp package is also available upon request. the drawing is provided on the following page.
AL128 april 2, 1999 43
AL128 april 2, 1999 44 11.0 power consumption the AL128 works at +5v or +3.3v, but the support of input resolution and refresh rate may be limited at the lower power. for full functionality of the AL128, the power needs to be more than +3.8v. at +3.3v, the AL128 can only support 640x480 resolution up to 85hz and 800x600 resolution up to 60hz. the following table shows the current consumption of the AL128 at different supply voltages. +5v +3.8v +3.3v (800x600 @60hz) normal 330ma 230ma 130ma power down 90ma 35ma 10ma please be reminded that when lower power supply is used, the pull-down resistance to the rset pin has to be adjusted to compensate (in both y/c/composite mode and rgb mode) accordingly. the lower the supply voltage is, the lower the pull-down resistance has to be. the ideal resistance values can be achieved by adjusting the y/c/composite output to be 1v peak-to-peak, or the rgb output to be 0.7v peak-to-peak.
contact information averlogic technologies, inc. 6840 via del oro suite 160 san jose, ca 95119 usa tel : 1 408 361-0400 fax : 1 408 361-0404 e-mail : sales@averlogic.com url : http://www.averlogic.com

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